We are looking for an experienced and passionate Principal Engineer / Technical Lead to join our team. In this role, you will be responsible for hands-on technical work while creating & managing the front-to-back design for our cutting-edge wireless infrastructure SOCs (5g-6g+), from architecture & RTL through logic design.
Key Responsibilities:
- Create and manage digital designs for SOCs from architecture and RTL to logic design
- Utilize tools such as Verification, Mixed Signal, Power Management, Synthesis, static timing, SystemVerilog, ATPG, Fault Grading, SCAN, Clock-domain, BIST, DFM, TCL, Python, Wireless, Amba, Protocol Bus Architecture, DFT, ARM/RISC, AXI/AHB/APB, Multi-core CPU, VHDL/Verilog and Fault Coverage Analysis
- Develop and implement strategies to improve the performance of the digital design process
- Work with stakeholders to ensure customer satisfaction and customer requirements
- Analyze and interpret digital network and system data to identify areas of improvement
- Develop and maintain documentation for processes, procedures and design standards
- Stay abreast of the latest digital design trends and techniques
- Identify areas of risk and take corrective action to mitigate them
Qualifications:
- MS / PhD in Electrical Engineering, Computer Engineering or related field
- Proven experience in digital design, architecture, RTL, and logic design
- Hands on experience with AMBA AXI/APB/AHB protocol bus architecture specs & implementations
- Some wireless experience - i.e. WiFi, iOT, Bluetooth, 4G, 5G, etc.
- Verilog, VHDL & System Verilog language experience & tools like linting, simulation, formal verification, clock-domain crossing checking, etc.
- ARM/RISC architecture, multi-core CPU system memory & operation hierarchy experience
- UVM/OVM methodology & language (SystemVerilog) experience
- Ability to manage multiple projects with tight deadlines
- Programming & Scripting experience - i.e. C/C++, Tcl, Python, Perl, awk, sed, etc.
- Excellent leadership experience & technical capabilities, wear multiple hats
- Nice to have skills & tech include: Verification, Mixed Signal, Power Management, Synthesis, static timing, SystemVerilog, ATPG, Fault Grading, SCAN, Clock-domain, BIST, DFM, TCL, Python,
Benefits
Base Pay, Pre-IPO equity, Health, Dental, Vision, 401k
Jason Kuna is recruiting for this position and the positions below.
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